Semiconductor device and method of fabricating the same

ABSTRACT

According to the present invention, there is provided a semiconductor device fabrication method comprising:
         forming a first insulating film on a semiconductor substrate;   forming a first conductive layer on the first insulating film;   forming a second insulating film on the first conductive layer in a first processing chamber isolated from an outside;   performing a modification process on the second insulating film in the first processing chamber, and unloading the semiconductor substrate from the first processing chamber to the outside;   annealing the second insulating film in a second processing chamber; and   forming a second conductive layer on the second insulating film.

CROSS REFERENCE TO RELATED APPLICATION

This application is based upon and claims benefit of priority under 35USC §119 from the Japanese Patent Application No. 2005-15415, filed onJan. 24, 2005, the entire contents of which are incorporated herein byreference.

BACKGROUND OF THE INVENTION

The present invention relates to a semiconductor device and a method offabricating the same.

Conventionally, a NAND flash memory has been developed as a nonvolatilesemiconductor memory. A memory cell transistor of this NAND flash memoryhas a structure in which a floating gate electrode formed on asemiconductor substrate via a tunnel insulating film and a control gateelectrode formed on this floating gate electrode via an inter-electrodeinsulating film are stacked.

Recently, to decrease the cell size, a method of using an alumina(Al₂O₃) film, instead of the conventional ONO film (a stacked film inwhich a silicon oxide film, silicon nitride film, and silicon oxide filmare stacked), as an inter-electrode insulating film is proposed(reference 1).

Since the alumina (Al₂O₃) film is a high-dielectric-constant film havinga relative dielectric constant higher than that of the ONO film, thearea of the inter-electrode insulating film can be reduced. As aconsequence, the cell size can be decreased.

The NAND flash memory stores “1” data in the memory cell transistor bydischarging electrons from the floating gate electrode to thesemiconductor substrate, and stores “0” data in the memory celltransistor by injecting electrons into the floating gate electrode fromthe semiconductor substrate.

Unfortunately, the density of a high-dielectric-constant film is low.Therefore, if a high-dielectric-constant film is used as theinter-electrode insulating film, electrons injected into the floatinggate electrode from the semiconductor substrate by applying an electricfield of a predetermined level between the control gate electrode andsemiconductor substrate penetrate through the inter-electrode insulatingfilm. This increases a leakage current flowing through the control gateelectrode.

To prevent this, therefore, it is necessary to suppress the leakagecurrent by performing a predetermined heating process (annealing) for ahigh-dielectric-constant film deposited on a conductive layer serving asthe floating gate electrode, thereby modifying thehigh-dielectric-constant film.

The reference concerning the use of the alumina (Al₂O₃) film as theinter-electrode insulating film is as follows.

-   Reference 1: Symposium on VLSI Technology Digest of Technical    Papers, p. 117, 1997

SUMMARY OF THE INVENTION

According to one aspect of the invention, there is provided asemiconductor device fabrication method comprising:

forming a first insulating film on a semiconductor substrate;

forming a first conductive layer on the first insulating film;

forming a second insulating film on the first conductive layer in afirst processing chamber isolated from an outside;

performing a modification process on the second insulating film in thefirst processing chamber, and unloading the semiconductor substrate fromthe first processing chamber to the outside;

annealing the second insulating film in a second processing chamber; and

forming a second conductive layer on the second insulating film.

According to one aspect of the invention, there is provided asemiconductor device fabrication method comprising:

loading a semiconductor substrate into a first processing chamberisolated from an outside, and forming an insulating film on a surface ofthe semiconductor substrate in the first processing chamber;

performing a modification process on the insulating film in the firstprocessing chamber, and unloading the semiconductor substrate from thefirst processing chamber to the outside;

annealing the insulating film in a second processing chamber; and

forming a conductive layer on the insulating film.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A and 1B are longitudinal sectional views each showing thesectional structure of elements in one step of a method of fabricating aNAND flash memory according to the first embodiment of the presentinvention;

FIGS. 2A and 2B are longitudinal sectional views each showing thesectional structure of elements in one step of the method of fabricatingthe NAND flash memory;

FIGS. 3A and 3B are longitudinal sectional views each showing thesectional structure of elements in one step of the method of fabricatingthe NAND flash memory;

FIGS. 4A and 4B are longitudinal sectional views each showing thesectional structure of elements in one step of the method of fabricatingthe NAND flash memory;

FIGS. 5A and 5B are longitudinal sectional views each showing thesectional structure of elements in one step of the method of fabricatingthe NAND flash memory;

FIGS. 6A and 6B are longitudinal sectional views each showing thesectional structure of elements in one step of the method of fabricatingthe NAND flash memory;

FIG. 7 is a block diagram showing the arrangement of a batch typedeposition/modification apparatus and annealing apparatus;

FIGS. 8A and 8B are longitudinal sectional views showing the sectionalstructure of a memory cell transistor according to the first embodimentof the present invention and that of a memory cell transistor of acomparative example;

FIG. 9 is a longitudinal sectional view showing the sectional structureof a floating gate electrode and vicinity in the memory cell transistorof the comparative example;

FIG. 10 is a longitudinal sectional view showing the sectional structureof the corner and vicinity at the upper end of the floating gateelectrode in the memory cell transistor of the comparative example;

FIG. 11 is a longitudinal sectional view showing the sectional structureof the floating gate electrode in the memory cell transistor;

FIG. 12 is a longitudinal sectional view showing the sectional structureof the interface and vicinity between the floating gate electrode and aninter-electrode insulating film in the memory cell transistor of thecomparative example;

FIG. 13 is a block diagram showing the arrangement of a single-waferdeposition/modification apparatus and annealing apparatus;

FIG. 14 is a longitudinal sectional view showing the sectional structureof elements in a predetermined step of a method of fabricating a MOSFETaccording to the second embodiment of the present invention;

FIG. 15 is longitudinal sectional views each showing the sectionalstructure of elements in one step of the method of fabricating theMOSFET;

FIG. 16 is longitudinal sectional views each showing the sectionalstructure of elements in one step of the method of fabricating theMOSFET;

FIG. 17 is longitudinal sectional views each showing the sectionalstructure of elements in one step of the method of fabricating theMOSFET;

FIG. 18 is longitudinal sectional views each showing the sectionalstructure of elements in one step of the method of fabricating theMOSFET; and

FIGS. 19A and 19B are longitudinal sectional views showing the sectionalstructure of the MOSFET according to the second embodiment of thepresent invention and that of a MOSFET of a comparative example.

DETAILED DESCRIPTION OF THE INVENTION

Embodiments of the present invention will be described below withreference to the accompanying drawings.

(1) First Embodiment

FIGS. 1A to 6B show a method of fabricating a memory cell transistor ofa NAND flash memory according to the first embodiment of the presentinvention. Of FIGS. 1A to 5B, each of FIGS. 1A, 2A, 3A, 4A, and 5A is alongitudinal sectional view, cut along a bit line, of elements in apredetermined step, and each of FIGS. 1B, 2B, 3B, 4B, and 5B is alongitudinal sectional view, cut along a word line, of elements in apredetermined step.

First, as shown in FIGS. 1A and 1B, a silicon oxynitride (SiON) film 20about 10 nm thick serving as a tunnel insulating film is formed bythermal oxidation and thermal nitriding on a semiconductor substrate 10into which a predetermined impurity is doped. After that, a phosphorous(P)-doped polysilicon layer 30 serving as a floating gate electrode isdeposited by CVD (Chemical Vapor Deposition), and a mask material 40 isformed by coating. Note that any of various impurities such as arsenic(As) may also be doped, in place of phosphorus (P), into the polysiliconlayer 30.

The mask material 40, polysilicon layer 30, and silicon oxynitride(SiON) film 20 are sequentially patterned by lithography and RIE(Reactive Ion Etching). In addition, the mask material 40 is used as amask to etch the semiconductor substrate 10, thereby forming an elementisolation trench 50 about 100 nm deep from the surface of thesemiconductor substrate 10.

As shown in FIGS. 2A and 2B, a silicon oxide film 60 is deposited on allthe surfaces of the semiconductor substrate 10 and mask material 40 soas to fill the element isolation trench 50. After that, the siliconoxide film 60 is planarized by polishing its surface by CMP (ChemicalMechanical Polishing), thereby forming a silicon oxide film 60 as anelement isolation insulating film.

As shown in FIGS. 3A and 3B, a predetermined amount of the surfaceportion of the silicon oxide film 60 is etched to be removed by using adilute hydrofluoric acid solution to expose the side surfaces of thepolysilicon layer 30 by about 50 nm. The exposed mask material 40 isthen selectively removed.

In addition, dilute hydrofluoric acid is used to remove a natural oxidefilm formed on the surface of the polysilicon layer 30. After that, thesemiconductor substrate 10 is loaded into a batch typedeposition/modification apparatus 65 shown in FIG. 7 which is aprocessing chamber having a single processing vessel and is called afurnace. In the deposition/modification apparatus 65, an alumina (Al₂O₃)film 70 serving as an inter-electrode insulating film is deposited onall the surfaces of the silicon oxide film 60 and polysilicon layer 30at a temperature of 400° C. Note that the deposition/modificationapparatus 65 has an exhausting mechanism and gas supply source (neitheris shown), and can form a desired ambient by using them.

In this embodiment, the alumina (Al₂O₃) film 70 is deposited as aninter-electrode insulating film. However, it is also possible to depositany of various high-dielectric-constant films having a relativedielectric constant of 4 or more. Examples are oxide films such ashafnia (HfO₂), zirconia (ZrO₂), hafnium silicate (HfSiO), and zirconiumsilicate (ZrSiO), and oxide films obtained by doping an impurity intothese oxide films.

When the alumina (Al₂O₃) film 70 which is a high-dielectric-constantfilm is used as an inter-electrode insulating film as in thisembodiment, it must be densified by high-temperature annealing in orderto suppress a leakage current in it.

Unfortunately, the deposition/modification apparatus 65 in which thealumina (Al₂O₃) film 70 is deposited cannot perform thishigh-temperature annealing. Therefore, it is necessary to once removethe semiconductor substrate 10 from the deposition/modificationapparatus 65, load the semiconductor substrate 10 into an annealingapparatus 75 shown in FIG. 7 which can perform high-temperatureannealing, and densify the alumina (Al₂O₃) film 70 by high-temperatureannealing in the annealing apparatus 75.

If, however, the semiconductor substrate 10 is exposed to the atmosphereafter being removed from the deposition/modification apparatus 65 andbefore being loaded into the annealing apparatus 75, the alumina (Al₂O₃)film 70 absorbs water.

If the alumina (Al₂O₃) film 70 which has absorbed water is annealed, alow-dielectric-constant silicon oxide film is formed in the interfacebetween the polysilicon layer 30 and alumina (Al₂O₃) film 70. This posesthe problem that the effective relative dielectric constant of thealumina (Al₂O₃) film 70 lowers.

In this embodiment, therefore, in the deposition/modification apparatus65 in which the alumina (Al₂O₃) film 70 is deposited, the alumina(Al₂O₃) film 70 is annealed in a nitrogen ambient at a temperature of,e.g., 800° C. for 60 min, thereby modifying, e.g., densifying thealumina (Al₂O₃) film 70 to such an extent that it does not absorb waterwhen the semiconductor substrate 10 is exposed to the atmosphere.

Note that the temperature of this annealing need only be, e.g., 600° C.to 900° C. which is higher than the temperature when the alumina (Al₂O₃)film 70 is deposited. However, the temperature is desirably as high aspossible because the densifying effect improves. Annealing may also beperformed in an oxidizing ambient, and the annealing time may also beabout 30 min.

After that, the semiconductor substrate 10 is removed from thedeposition/modification apparatus 65, and loaded into the annealingapparatus 75 shown in FIG. 7. Although the semiconductor substrate 10 isexposed to the atmosphere during this transfer, it is possible tosuppress the alumina (Al₂O₃) film 70 from absorbing water, i.e.,suppress moisture absorption by the alumina (Al₂O₃) film 70.

In the annealing apparatus 75, the alumina (Al₂O₃) film 70 is annealedin an oxidizing ambient at, e.g., about 1,035° C. which is higher thanthe temperature of annealing for suppressing moisture absorption by thealumina (Al₂O₃) film 70, without performing any liquid chemicaltreatment for avoiding moisture absorption by the alumina (Al₂O₃) film70, thereby densifying the alumina (Al₂O₃) film 70 to such an extentthat the leakage current in it can be suppressed. After that, thesemiconductor substrate 10 is removed from the annealing apparatus 75.

Note that if a high-dielectric-constant film is deposited as a tunnelinsulating film, the densifying process described above may also beapplied to this tunnel insulating film.

As shown in FIGS. 4A and 4B, CVD is performed to deposit a conductivelayer 80 about 100 nm thick which has a two-layered structure including,e.g., a polysilicon layer and tungsten (W) silicide layer, and whichserves as a control gate electrode later, and to deposit a mask material90.

The mask material 90, conductive layer 80, alumina (Al₂O₃) film 70,polysilicon layer 30, and silicon oxynitride (SiON) film 20 aresequentially patterned by lithography and RIE, thereby forming a slit100. In this manner, a floating gate electrode made of the polysiliconlayer 30 and a control gate electrode made of the conductive layer 80are formed.

As shown in FIGS. 5A and 5B, a silicon oxide film 100 serving as anelectrode sidewall insulating film is formed by thermal oxidation on theexposed surfaces of the semiconductor substrate 10, silicon oxynitride(SiON) film 20, polysilicon layer 30, alumina (Al₂O₃) film 70,conductive layer 80, and mask material 90. After that, a source region110A and drain region 110B are formed by ion implantation, and aninterlayer dielectric film 120 is formed on the entire surface of thesilicon oxide film 100 by CVD. Finally, interconnecting layers (notshown) and the like are formed to fabricate the memory cell transistorof the NAND flash memory.

FIG. 6A shows the longitudinal section when a NAND flash memory 200 inwhich memory cell transistors MC fabricated by the above method arearranged in a matrix is cut along a bit line BL. FIG. 6B shows thecircuit diagram, which corresponds to the longitudinal section shown inFIG. 6A, of the NAND flash memory 200.

In the NAND flash memory 200 as shown in FIGS. 6A and 6B, the sourceregions 110A and drain regions 110B of a plurality of memory celltransistors MC are connected in series between two selection transistors(not shown), one of these selection transistors is connected to the bitline BL, and the other is connected to a source line (not shown). Also,a word line WL is connected to the control gate electrode made of theconductive layer 80 of each memory cell transistor MC.

In this embodiment, the NAND flash memory 200 is fabricated as a flashmemory. However, it is also possible to fabricate any of various flashmemories having a structure in which a floating gate electrode andcontrol gate electrode, e.g., NOR and AND are stacked. Furthermore, astructure including three or more stacked layers each made up of aninsulating film and gate electrode may also be formed.

FIG. 8A shows the structure of the memory cell transistor MC of the NANDflash memory 200 according to this embodiment. FIG. 8B shows thestructure of a memory cell transistor MC10 as a comparative example. Inthe memory cell transistor MC10, an alumina (Al₂O₃) film 70 is notdensified after being deposited, but densified after being exposed tothe atmosphere, thereby forming a low-dielectric-constant silicon oxidefilm 210 in the interface between a floating gate electrode made of apolysilicon layer 30 and an inter-electrode insulating film made of thealumina (Al₂O₃) film 70.

The memory cell transistor MC10 of the comparative example has theproblem that the effective relative dielectric constant of theinter-electrode insulating film lowers, since thelow-dielectric-constant silicon oxide film 210 is formed in theinterface between the floating gate electrode made of the polysiliconlayer 30 and the inter-electrode insulating film made of the alumina(Al₂O₃) film 70.

By contrast, in this embodiment, in the deposition/modificationapparatus 65, the alumina (Al₂O₃) film 70 is densified, after beingdeposited and before being exposed to the atmosphere, to such an extentthat moisture absorption by the alumina (Al₂O₃) film 70 can besuppressed. Accordingly, even when the alumina (Al₂O₃) film 70 isdensified in the annealing apparatus 75 to such an extent that theleakage current in the alumina (Al₂O₃) film 70 can be suppressed, it ispossible to prevent the formation of the low-dielectric-constant siliconoxide film 210 in the interface between the polysilicon layer 30 andalumina (Al₂O₃) film 70. This makes it possible to suppress the loweringof the effective relative dielectric constant of the alumina (Al₂O₃)film 70 as a high-dielectric-constant film.

Also, as shown in FIG. 8B, if the low-dielectric-constant silicon oxidefilm 210 is formed in the interface between the polysilicon layer 30 andalumina (Al₂O₃) film 70 as in the memory cell transistor MC10 of thecomparative example, the existence of the silicon oxide film 210increases the leakage current (an arrow A10 in FIG. 8B) in the alumina(Al₂O₃) film 70 as an inter-electrode insulating film.

That is, when an electric field of a predetermined level is appliedbetween a conductive layer 80 as the control gate electrode and asemiconductor substrate 10 to inject electrons (an arrow A20 in FIG. 8B)from the semiconductor substrate 10 into the polysilicon layer 30 as thefloating gate electrode, these electrons injected into the polysiliconlayer 30 penetrate through the silicon oxide film 210 and alumina(Al₂O₃) film 70, and increase the leakage current (the arrow A10 in FIG.8B) flowing through the conductive layer 80.

Conversely, in this embodiment as shown in FIG. 8A, it is possible toprevent the formation of the low-dielectric-constant silicon oxide film210 in the interface between the polysilicon layer 30 and alumina(Al₂O₃) film 70. Therefore, even when an electric field of apredetermined level is applied between the conductive layer 80 andsemiconductor substrate 10 to inject electrons (an arrow A30 in FIG. 8A)from the semiconductor substrate 10 into the polysilicon layer 30, aleakage current in the alumina (Al₂O₃) film 70 can be suppressed.

Also, as shown in FIG. 9, in the memory cell transistor MC10 of thecomparative example, the silicon oxide film 210 is formed into aninverse U-shape along the interface between the polysilicon layer 30 asthe floating gate electrode and the alumina (Al₂O₃) film 70 as theinter-electrode insulating film.

When a length W in the direction of the word line WL of the surface ofthe polysilicon layer 30 shortens by the film thickness of the siliconoxide film 210, the surface area of the polysilicon layer 30 reduces. Asa consequence, the capacitance of the capacitor between the conductivelayer 80 and polysilicon layer 30 decreases.

This causes the necessity of the higher voltage applied to theconductive layer 80 as the control gate electrode to inject electronsfrom the semiconductor substrate 10 into polysilicon layer 30 as thefloating gate electrode, and then the larger electric filed is appliedbetween the conductive layer 80 and polysilicon layer 30.

Recently, the dimension (i.e., the channel width) W in the direction ofthe word line WL of the surface of the polysilicon layer 30 is set to100 nm or less, and desirably, 50 nm or less, by the decrease in cellsize.

Accordingly, when the silicon oxide film 210 is formed along theinterface between the polysilicon layer 30 and alumina (Al₂O₃) film 70,the influence the silicon oxide film 210 has on the surface area of thepolysilicon layer 30 increases, so the memory cell transistorcharacteristics largely change.

On the contrary, in this embodiment, it is possible to prevent theformation of the silicon oxide film 210 along the interface between thepolysilicon layer 30 and alumina (Al₂O₃) film 70. This suppresses thechange in memory cell transistor characteristics.

Also, as shown in FIG. 10, when the silicon oxide film 210 is formedinto an inverse U-shape along the interface between the polysiliconlayer 30 as the floating gate electrode and the alumina (Al₂O₃) film 70as the inter-electrode insulating film as in the memory cell transistorMC10 of the comparative example, a corner 30A at the upper end of thepolysilicon layer 30 is pointed because the oxidation rate is low inthis portion.

When, therefore, a high electric field is applied between the conductivelayer 80 as the control gate electrode and the polysilicon layer 30 asthe floating gate electrode, field concentration occurs in the corner30A at the upper end of the polysilicon layer 30 because the corner 30Ais pointed. This allows easy occurrence of insulation breakdown.

By contrast, in this embodiment, it is possible to prevent the formationof the silicon oxide film 210 along the interface between thepolysilicon layer 30 and alumina (Al₂O₃) film 70. This prevents theoccurrence of insulating breakdown caused by field concentration in thecorner 30A at the upper end of the polysilicon layer 30.

Furthermore, to prevent the formation of a depletion layer when anelectric field is applied, the polysilicon layer 30 serving as thefloating gate electrode is formed such that the impurity concentrationof, e.g., phosphorus (P) doped is as high as, e.g., 1.0×10²⁰/cm³ ormore.

In this case, if the silicon oxide film 210 having a high impurityconcentration is formed in the interface between the polysilicon layer30 and alumina (Al₂O₃) film 70 as in the memory cell transistor MC10 ofthe comparative example, the leakage current in the alumina (Al₂O₃) film70 as an electrode insulating film increases compared to the case inwhich a silicon oxide film having a low impurity concentration isformed.

In contrast to this, in this embodiment, it is possible to prevent theformation of the silicon oxide film 210 having a high impurityconcentration in the interface between the polysilicon layer 30 andalumina (Al₂O₃) film 70. This suppresses the increase of the leakagecurrent in the alumina (Al₂O₃) film 70 as an electrode insulating film.

Also, as shown in FIG. 11, the polysilicon layer 30 as the floating gateelectrode is made of polysilicon having a plurality of single-crystalgrains 30B. Therefore, as shown in FIG. 12, when the silicon oxide film210 is formed in the interface between the polysilicon layer 30 andalumina (Al₂O₃) film 70 as in the memory cell transistor MC10 of thecomparative example, oxygen diffuses along a grain boundary 30C.Consequently, a projecting portion 210A which sharply projects along thegrain boundary 30C is formed on the silicon oxide film 210.

Accordingly, when an electric field is applied between the conductivelayer 80 as the control gate electrode and the polysilicon layer 30 asthe floating gate electrode, field concentration occurs in theprojecting portion 210A of the silicon oxide film 210, and thisincreases the leakage current.

On the contrary, in this embodiment, it is possible to prevent theformation of the silicon oxide film 210 in the interface between thepolysilicon layer 30 and alumina (Al₂O₃) film 70. This suppresses theincrease of the leakage current caused by field concentration near thegrain boundary 30C of the single-crystal grains 30B.

Note that the first embodiment described above is merely an example, andhence does not limit the present invention. For example, in the batchtype deposition/modification apparatus 65 called a furnace, the alumina(Al₂O₃) film 70 is deposited, and annealing is performed to suppressmoisture absorption by the alumina (Al₂O₃) film 70. However, it is alsopossible to perform deposition of the alumina (Al₂O₃) film 70 andannealing for suppressing moisture absorption in a single-wafer typedeposition/modification apparatus 220 called a cluster chamber shown inFIG. 13.

A transfer chamber 230 is placed near the central portion of thedeposition/modification apparatus 220 as a processing chamber called acluster chamber. A loading chamber 240, an unloading chamber 250, adeposition chamber 260 as a processing vessel, and an annealing chamber270 as another processing vessel are arranged around the transferchamber 230.

A transfer mechanism 280 which is an arm or the like is placed near thecentral portion of the transfer chamber 230, and transfers thesemiconductor substrate 10 between the chambers 240 to 270. Also, thetransfer chamber 230 has an exhausting mechanism and gas supply source(neither is shown), and a desired ambient is formed in the transferchamber 230 by using them. In this manner, the semiconductor substrate10 can be transferred to a desired chamber without being exposed to theatmosphere.

That is, the transfer mechanism 280 of the transfer chamber 230transfers the semiconductor substrate 10 loaded from the loading chamber240 to the deposition chamber 260, and an alumina (Al₂O₃) film 70 isdeposited in the deposition chamber 260. After that, the semiconductorsubstrate 10 is transferred from the deposition chamber 260 to theannealing chamber 270 via the transfer chamber 230. In the annealingchamber 270, the alumina (Al₂O₃) film 70 is densified by annealing tosuch an extent that moisture absorption by the alumina (Al₂O₃) film 70can be suppressed.

Then, the semiconductor substrate 10 is transferred from the annealingchamber 270 to the unloading chamber 250 via the transfer chamber 230,and thereby removed from the deposition/modification apparatus 220. Thesemiconductor substrate 10 is loaded into an annealing apparatus 290shown in FIG. 13. Although the semiconductor substrate 10 is exposed tothe atmosphere during this transfer as in the above first embodiment,moisture absorption by the alumina (Al₂O₃) film 70 can be suppressed.

In the annealing apparatus 290, the alumina (Al₂O₃) film 70 is densifiedby annealing at a high temperature to such an extent that the leakagecurrent in the alumina (Al₂O₃) film 70 can be suppressed.

(2) Second Embodiment

FIGS. 14 to 18 show a method of fabricating a MOSFET according to thesecond embodiment of the present invention. First, as shown in FIG. 14,element isolation insulating films 310A and 310B are formed on asemiconductor substrate 300, and a natural oxide film formed on thesemiconductor substrate 300 is removed by cleaning using dilutehydrofluoric acid.

As shown in FIG. 15, the semiconductor substrate 300 is loaded into abatch type deposition/modification apparatus 65 shown in FIG. 7 which isa processing chamber having a single processing vessel and is called afurnace. In the deposition/modification apparatus 65, a hafnia (HfO₂)film 320 serving as a gate insulting film is deposited on the surface ofthe semiconductor substrate 300 at a temperature of 400° C. Note thatthe deposition/modification apparatus 65 has an exhausting mechanism andgas supply source (neither is shown), and can form a desired ambient byusing them.

In this embodiment, the hafnia (HfO₂) film 320 is deposited as a gateinsulating film. However, it is also possible to deposit any of varioushigh-dielectric-constant films having a relative dielectric constant of4 or more. Examples are oxide films such as alumina (Al₂O₃), zirconia(ZrO₂), hafnium silicate (HfSiO), and zirconium silicate (ZrSiO), andoxide films obtained by doping an impurity into these oxide films.

As in the first embodiment, in the deposition/modification apparatus 65in which the hafnia (HfO₂) film 320 is deposited, the hafnia (HfO₂) film320 is densified by annealing in a nitrogen ambient at a temperature of,e.g., 800° C., to such an extent that the hafnia (HfO₂) film 320 doesnot absorb water when the semiconductor substrate 300 is exposed to theatmosphere.

Note that, as in the first embodiment, the temperature of this annealingneed only be, e.g., 600° C. to 900° C. which is higher than thetemperature when the hafnia (HfO₂) film 320 is deposited. However, thetemperature is desirably as high as possible because the densifyingeffect increases. Annealing may also be performed in an oxidizingambient.

After that, the semiconductor substrate 300 is removed from thedeposition/modification apparatus 65, and loaded into an annealingapparatus 75 shown in FIG. 7. Although the semiconductor substrate 300is exposed to the atmosphere during this transfer, it is possible tosuppress the hafnia (HfO₂) film 320 from absorbing water, i.e., suppressmoisture absorption by the hafnia (HfO₂) film 320.

In the annealing apparatus 75, the hafnia (HfO₂) film 320 is annealed inan oxidizing ambient at, e.g., about 1,000° C. which is higher than thetemperature of annealing for suppressing moisture absorption by thehafnia (HfO₂) film 320, without performing any liquid chemicaltreatment, thereby densifying the hafnia (HfO₂) film 320 to such anextent that the leakage current in the hafnia (HfO₂) film 320 can besuppressed. After that, the semiconductor substrate 300 is removed fromthe annealing apparatus 75.

As shown in FIG. 16, CVD is performed to deposit a polysilicon layer 330serving as a gate electrode. As shown in FIG. 17, the polysilicon layer330 and hafnia (HfO₂) film 320 are sequentially patterned by lithographyand RIE, thereby forming a gate insulating film made of the hafnia(HfO₂) film 320, and a gate electrode made of the polysilicon layer 330.As shown in FIG. 18, a source region 340A and drain region 340B areformed by ion implantation. In this manner, a MOSFET 400 is fabricated.

FIG. 19A shows the structure of the MOSFET 400 according to thisembodiment. FIG. 19B shows the structure of a MOSFET 500 as acomparative example. In the MOSFET 500, a hafnia (HfO₂) film 320 is notdensified after being deposited, but densified after being exposed tothe atmosphere, thereby forming a low-dielectric-constant silicon oxidefilm 510 in the interface between a gate insulating film made of thehafnia (HfO₂) film 320 and a semiconductor substrate 300.

The MOSFET 500 of the comparative example has the problem that theeffective relative dielectric constant of the gate insulating filmlowers, since the low-dielectric-constant silicon oxide film 510 isformed in the interface between the gate insulating film made of thehafnia (HfO₂) film 320 and the semiconductor substrate 300.

By contrast, in this embodiment, as in the first embodiment, the hafnia(HfO₂) film 320 is densified in the deposition/modification apparatus65, after being deposited and before being exposed to the atmosphere, tosuch an extent that moisture absorption by the hafnia (HfO₂) film 320can be suppressed. Accordingly, even when the hafnia (HfO₂) film 320 isdensified in the annealing apparatus 75 to such an extent that theleakage current in the hafnia (HfO₂) film 320 can be suppressed, it ispossible to prevent the formation of the low-dielectric-constant siliconoxide film 510 in the interface between the hafnia (HfO₂) film 320 andsemiconductor substrate 300. This makes it possible to suppress thelowering of the effective relative dielectric constant of the hafnia(HfO₂) film 320 as a high-dielectric-constant film.

Also, as shown in FIG. 19B, if the low-dielectric-constant silicon oxidefilm 510 is formed in the interface between the hafnia (HfO₂) film 320and semiconductor substrate 300 as in the MOSFET 500 of the comparativeexample, the existence of the silicon oxide film 510 increases theleakage current (an arrow A100 in FIG. 19B) in the hafnia (HfO₂) film320 as a gate insulating film.

That is, when an electric field of a predetermined level is appliedbetween the polysilicon layer 330 as the gate electrode and thesemiconductor substrate 300 to draw electrons toward the surface of thesemiconductor substrate 300, these drawn electrons penetrate through thesilicon oxide film 510 and hafnia (HfO₂) film 320, and increase theleakage current (the arrow A100 in FIG. 19B) flowing through thepolysilicon layer 330.

Conversely, in this embodiment as shown in FIG. 19A, it is possible toprevent the formation of the low-dielectric-constant silicon oxide film510 in the interface between the hafnia (HfO₂) film 320 andsemiconductor substrate 300. Therefore, the leakage current in thehafnia (HfO₂) film 320 can be suppressed.

Note that the second embodiment described above is merely an example,and hence does not limit the present invention. For example, in thebatch type deposition/modification apparatus 65 called a furnace, thehafnia (HfO₂) film 320 is deposited, and annealing is performed tosuppress moisture absorption by the hafnia (HfO₂) film 320. However, asin the other embodiment of the first embodiment, it is also possible toperform deposition of the hafnia (HfO₂) film 320 and annealing forsuppressing moisture absorption in a single-wafer typedeposition/modification apparatus 220 called a cluster chamber shown inFIG. 13.

In this case, as in the other embodiment of the first embodiment, thesemiconductor substrate 300 is removed from the deposition/modificationapparatus 220 which is a processing chamber having a plurality ofprocessing vessels, and loaded into an annealing apparatus 290 shown inFIG. 13. Although the semiconductor substrate 300 is exposed to theatmosphere during this transfer, moisture absorption by the hafnia(HfO₂) film 320 can be suppressed.

In the annealing apparatus 290, the hafnia (HfO₂) film 320 is densifiedby annealing at a high temperature to such an extent that the leakagecurrent in the hafnia (HfO₂) film 320 can be suppressed.

(3) Other Embodiments

Note that the first and second embodiments described above are merelyexamples, and hence do not limit the present invention. For example,oxygen radical processing may also be performed at a temperature of 400°C. as the modification process of suppressing moisture absorption by thealumina (Al₂O₃) film 70 and hafnia (HfO₂) film 320. In this case,although the temperature need only range from room temperature to 900°C., the temperature is desirably as high as possible because themodification effect improves.

The oxygen radical is, e.g., neutral atomic oxygen or excited molecularoxygen, and is generated by changing a gas mixture, which is obtained bydiluting oxygen gas to 1% to 10% with argon gas, into plasma bymicrowaves. The alumina (Al₂O₃) film 70 and hafnia (HfO₂) film 320 aremodified by oxygen radical processing which causes the alumina (Al₂O₃)film 70 and hafnia (HfO₂) film 320 to absorb this oxygen radical.

Note that this oxygen radical processing may also be performed in anambient in which the oxygen radical and oxygen ion are mixed. It is alsopossible to dilute oxygen gas with any of various diluent gases such ashelium, neon, krypton, and xenon. Furthermore, the ratio of oxygen gasmay also be increased by reducing the amount diluted by the diluent gas,or the ratio of oxygen gas may also be set at 100% without any dilutionby the diluent gas.

Although hydrogen gas may also be added to the gas mixture, the additionamount is preferably as low as 1% to 10%. The gas mixture may also bechanged into plasma by a high frequency, NO gas, or N₂O gas, instead ofmicrowaves. The oxygen radical may also be generated by the reaction ofoxygen gas with hydrogen gas.

Nitrogen radical processing may also be performed by generating nitrogenradical by changing a gas mixture of nitrogen gas and a diluent gas or100% nitrogen gas into plasma by the same method as for generating theoxygen radical. It is also possible to simultaneously perform the oxygenradical processing and nitrogen radical processing by simultaneouslygenerating the oxygen radical and nitrogen radical by changing a gasmixture of oxygen gas and nitrogen gas into plasma.

Furthermore, as the modification process of suppressing moistureabsorption by the alumina (Al₂O₃) film 70 and hafnia (HfO₂) film 320, itis also possible to perform an ultraviolet radiation process ofirradiating the alumina (Al₂O₃) film 70 and hafnia (HfO₂) film 320 withultraviolet light in a nitrogen ambient at room temperature.

Note that a light radiation process of radiating any of various types oflight such as visible light, infrared light, and white light may also beperformed.

In this case, a point light source is placed above the semiconductorsubstrates 10 and 300, and the semiconductor substrates 10 and 300 areirradiated, by uniform intensity, with light emitted from this pointlight source by using a light reflecting plate. It is also possible toarrange a plurality of light sources over the semiconductor substrates10 and 300, and irradiate the semiconductor substrates 10 and 300, byuniform intensity, with light emitted from these light sources.

Although the temperature need only range from room temperature to 900°C., the temperature is desirably as high as possible because themodification effect improves. The light radiation process may also beperformed in an oxygen ambient or in a vacuum, instead of a nitrogenambient.

As has been explained above, the semiconductor device fabrication methodof each of the above embodiments can improve the reliability of thesemiconductor device by suppressing the leakage current.

1. A semiconductor device fabrication method comprising: forming a firstinsulating film on a semiconductor substrate; forming a first conductivelayer on the first insulating film; forming a second insulating film onthe first conductive layer in a first processing chamber isolated froman outside; performing a modification process on the second insulatingfilm in the first processing chamber, and unloading the semiconductorsubstrate from the first processing chamber to the outside; annealingthe second insulating film in a second processing chamber; and forming asecond conductive layer on the second insulating film.
 2. A methodaccording to claim 1, wherein the first processing chamber comprises asingle processing vessel.
 3. A method according to claim 1, wherein arelative dielectric constant of the second insulating film is not lessthan
 4. 4. A method according to claim 1, wherein the modificationprocess is annealing performed at a temperature not less than atemperature when the second insulating film is formed, oxygen radicaland/or nitrogen radical processing, or a light radiation process.
 5. Amethod according to claim 1, further comprising, patterning the firstconductive layer and first insulating film, and etching to remove anexposed portion of the semiconductor substrate by a predetermined depth,thereby forming a trench such that a width of a projecting portionformed in a surface portion of the semiconductor substrate is not morethan 100 nm.
 6. A method according to claim 1, further comprising,patterning the first conductive layer and first insulating film, andetching to remove an exposed portion of the semiconductor substrate by apredetermined depth, thereby forming a trench such that a width of aprojecting portion formed in a surface portion of the semiconductorsubstrate is not more than 50 nm.
 7. A method according to claim 1,further comprising: patterning the first conductive layer and firstinsulating film, and etching away an exposed portion of thesemiconductor substrate by a predetermined depth, thereby forming atrench; filling the trench with a third insulating film; and etching toremove a predetermined amount of a surface portion of the thirdinsulating film to expose an upper portion of a side surface of thefirst conductive layer, which is in contact with the third insulatingfilm, wherein when the second insulating film is formed, the secondinsulating film is formed on the first conductive layer and thirdinsulating film.
 8. A method according to claim 1, wherein when thefirst conductive layer is formed, the first conductive layer whoseimpurity concentration is not less than 1.0×10²⁰/cm³ is formed.
 9. Amethod according to claim 1, wherein when the first conductive layer isformed, the first conductive layer is formed by depositing apolycrystalline semiconductor material.
 10. A method according to claim1, further comprising: forming a control gate electrode, inter-electrodeinsulating film, floating gate electrode, and tunnel insulating film bysequentially patterning the second conductive layer, second insulatingfilm, first conductive layer, and first insulating film; and forming asource region and drain region by ion-implanting a predeterminedimpurity into a surface portion of the semiconductor substrate.
 11. Amethod according to claim 1, wherein the semiconductor device is a NANDflash memory.
 12. A semiconductor device fabrication method comprising:loading a semiconductor substrate into a first processing chamberisolated from an outside, and forming an insulating film on a surface ofthe semiconductor substrate in the first processing chamber; performinga modification process on the insulating film in the first processingchamber, and unloading the semiconductor substrate from the firstprocessing chamber to the outside; annealing the insulating film in asecond processing chamber; and forming a conductive layer on theinsulating film.
 13. A method according to claim 12, wherein the firstprocessing chamber comprises a single processing vessel.
 14. A methodaccording to claim 12, wherein a relative dielectric constant of theinsulating film is not less than
 4. 15. A method according to claim 12,wherein the modification process is annealing performed at a temperaturenot less than a temperature when the insulating film is formed, oxygenradical and/or nitrogen radical processing, or a light radiationprocess.
 16. A method according to claim 12, further comprising: formingthe gate electrode and gate insulating film by sequentially patterningthe conductive layer and insulating film; and forming a source regionand drain region by ion-implanting a predetermined impurity by using thegate electrode as a mask.